The present invention is directed to large scale integrated circuit chips, and more particularly to wiring arrangements for such chips that reduce inductive crosstalk which might lead to signalling errors on the chip and provide for more uniform voltage distribution to the gates on the chip.
With the continuing advances in the areas of microelectronics and integrated circuit technology, the operating speed, size and circuit density of large scale integrated (LSI) and very large scale integrated (VLSI) logic chips are increasing all the time. Up to now, one phenomenon that has been given little or no consideration in the design of these chips, since it has posed no significant problems, has been the magnetic fields that are generated by current path loops on the chip. In smaller chips, e.g., those with less than 100 gates, these fields are so weak that they do not have a noticeable effect on signalling currents. However, as the speed and density of the circuits on the chip continue to be increased, this phenomenon becomes increasingly more important.
In a conventionally wired chip, the current is usually injected on to the chip through a bonding pad located at one corner of the chip or on one side thereof, and another bonding pad located at the diagonally opposite corner, or the opposite side of the chip, is connected to a ground reference potential to sink the current from the gates. Consequently, a current path is established from one corner or side of the chip to the opposite corner or side of the chip, which then loops around back to the pad through which the current is injected to encompass a substantial portion of the area of the chip. For example, referring to FIG. 1, an integrated circuit chip 10 can comprise a multiplicity of logic gates 12 which are each connected in parallel with one another between a power bus 14 and a ground bus 16. As depicted in FIG. 1, the logic gates 12 are divided into two rows and the power and ground busses are also divided into two parallel conductive runs, that are respectively connected to the two rows. However, it will be appreciated that the chip might have only one row of logic gates or a multiplicity of rows each being supplied by a separate conductive run. The particular number of rows of parallel connected logic gates will be determined by the circuit to be incorporated in the chip and the design layout principles that are utilized.
The chip of FIG. 1 embodies a conventional wiring arrangement for supplying current to, and sinking it from, the individual logic gates. More particularly, the power supply bus 14 is connected to a bonding pad 18 that is disposed at one corner of the chip. This pad is in turn connected to one of the pins in the chip package which is supplied with current from a suitable supply source. The ground bus 16 is similarly connected to a bonding pad 20 located on the diagonally opposite corner of the chip from the pad 18. The pad 20 is connected to a suitable ground reference potential through a connecting pin on the chip package.
In a slightly different wiring scheme, the current supply pad 18 can be located closer to the center of the top edge of the chip, and the current sinking pad can be located closer to the center of the bottom edge of the chip, rather than the pads being disposed on diagonally opposite corners.
In operation, the current flows from the bonding pad 18 through the various logic gates which are in a conductive state to the ground bus 16 and the bonding pad 20. The return path for the current is from the bonding pad 20 back to the pad 18 which are separated by at least the length of the diagonal dimension of the chip package. This current flow path is schematically indicated by the dashed lines in FIG. 1 for the case when one of the gates in the upper row of logic gates is conducting. Each gate which is at a conductive state will also establish a similar flow path. In actual practice, this return path is formed by the conductive runs on a printed circuit board (not shown) on which the chip is mounted. These runs lead from the connecting pins associated with the bonding pads 18 and 20 to edge connectors on the board which are hooked up to the power supply.
As can be seen, the area that is encompassed by the current loop comprises, at a minimum, a substantial portion of the area of the integrated circuit chip. During a clock cycle, the change in switching states of the logic gates on the chip might be substantial enough to cause a significant change in the amount of current flowing from the pad 18 to the pad 20, and the current induced in other on-chip conductors by the changing magnetic field could be substantial enough to generate logic errors. More particularly, during a clock cycle a number of gates can successively change states. A switching which occurs in a later stage of the series of gates can inductively trigger a change in state in an earlier stage during the same clock cycle, thus generating a logic error.
The possibility of such an occurrence increases with increased packing density of chips. For example, on a VSLI chip having 10.sup.6 gates, during a given clock cycle the number of gates switching in one direction might exceed the number of gates switching in the other direction by as much as 20,000. If it is assumed that the total current supplied to the chip is 25 amperes, such that each individual logic gate receives 25 microamps, a net change in state of 20,000 gates will result in the current flowing through the chip being increased or decreased by 1/2 ampere. Such a change, and more particularly, the electromotive force generated by such a change, can be significant when considering the relatively low voltage levels that are typically used in IC chips. For example, the difference between a logic high and a logic low state might be as low as 0.1 volt. If a magnetic field that is inductively generated by a current change is large enough, it may be possible to affect the voltage on the signal lines within the chip such that one logic state is improperly detected as being the other state, resulting in a logic error.
Since the total magnetic flux produced by the current loop is a product of the inductance and the current, it will be appreciated that if the inductance of the chip can be reduced the probability of logic errors that are caused by inductively generated magnetic fields will also be diminished.
The inductance L generated by a current loop can be defined as follows: ##EQU1## where: .mu..sub.o is the effective permeability of the region on the chip in which the associated magnetic field is present,
A is the area circumscribed by the current loop, and PA1 R is the mean radius of the loop.
As can be seen, the magnitude of the inductance is directly related to the area of the current loop. More appropriately, it is proportional to the mean radius of the loop (since A=.pi.R.sup.2). If the area within the current loop can be reduced, the probability of inductive interference between circuits can also be reduced, since the magnetic field intensity is directly proportional to the inductance for a given current level.